Tanner Tools 2019.2 | 2.0 Gb
Languages: english, 日本語, 中文 Simplified, 中文 Traditional
Mentor, a Siemens business, has unveiled Tanner Tools 2019.2 is a suite of tools for the design of integrated circuits. These tools allow you to enter schematics, perform SPICE simulations, do physical design (i.e., chip layout), and perform design rule checks (DRC) and layout versus schematic (LVS) checks.

Tanner Tools Release Notes - Date: 14 may 2019

Enhancements for S-Edit

ER 28812 — Images may now be inserted in symbol and schematic views. Both bitmap and vector formats are supported on Windows. Bitmap formats only are supported on Linux.
ER 44849 — S-Edit is now integrated with AFS, Eldo and EZwave to provide simulation setup, launching, cross probing and back annotation support in an all Linux environment. Setup and launching, cross probing and back annotation are now also supported with S-Edit on Windows and AFS/EZWave on Linux using the PSF output format. Back Annotation support includes DC OP V/I, AC small-signals, Model parameters, Device AC small-signal parameter tables, and Device parameter back annotation.
ER 45661 — S-Edit now provides support for inherited connections defined by parameterized power/ground symbols or by net labels.
ER 46410 — A script to set the bindkeys in S-Edit to match those in Cadence has been added in the shipping examples in the “Features By Tool\S-Edit\Bind Keys” directory.

Corrected Problems for S-Edit

DR 39757, 41513, 45595, 45729 — Improved placement and orientation of ports and net labels read from Cadence OA databases.Fixed problems where ports and net labels were disconnected from their wires and where net labels created unexpected 4-way connections. Also improved performance reading ports and net labels from Cadence OA.
DR 41013 — Improved Lib/Cell/View support in Calibre LVS. Fixed problem where the same cell name was in different libraries.
DR 44594 — A new Tcl command “database globalports’ is added. By specifying -cell 'cell name' the command returns all global ports used in the specified cell and its hierarchy.
DR 45219 — Fixed problems with Calibre LVS schematic crossprobing.
DR 45509 — The evi_worker, esi_worker, and nitro_worker scripts for Linux now explicitly call python2.
DR 45590 — Improvements in SDL Router for adding VIA breakouts to a port covered by OBS layer.
DR 45663 — Inherited connections with netlist procedures are now supported.
DR 45666 — Adding Libraries in place of Unresolved Libraries now works correctly.
DR 45679 — Fixed screen resizing problems for all tools on Linux under VNC.
DR 45695 — Expanded capacity of property value edit control in both Add User Property dialog and Edit Expression dialog to handle very long strings.
DR 45733 — The stability of auto-generated names has been improved; however, the names of auto-generated names are changed over previous versions.
DR 45751 — Cell Copy with hierarchy now copies CDF parameters.
DR 45752 — Fixed problem in Spice output when an inherited connection is used in an arrayed instance.
DR 45775 — The default severity of Design Check 19 - Dangling wire (named) is changed from Warning to Ignore

Enhancements for L-Edit

ER 38451 — Parameterized cell abutment is now available in L-Edit. This feature allows instances of parameterized cells, when abutted, to adjust their geometries to occupy minimum area. For example, if two instances of an n-channel MOSFET that share the same source or drain, abutment will regenerate the instances to remove additional contacts and bring these two devices very close to each other.
ER 42220 — L-Edit can now open an OA .defs file with any base name and .defs extension, file name does not have to be lib.defs.
ER 45171 — The fill pattern for Calibre highlighting can now be controlled using a TCL variable, tanner_calibre_highlight_fill, to set the fill pattern. The variable is a 64-bit integer and defines an 8x8 grid pattern, with 1 transparent and 0 filled. Due to a limitation in rendering, it can't be entirely filled, so setting the variable to 0 results in no fill. For example: set tanner_calibre_highlight_fill 0xF0F0F0F00f0f0f0f.
ER 46378 — LayoutForge is a productivity enhancing tool for analog layout designers performing device level placement and routing, allowing full control over the placement and routing. LayoutForge recognizes differential pairs, amplifiers, and current mirrors in schematic and automatically generates a placed and routed cell in layout. Designers can customize placement of devices, with center of moment assistance, and can customize routing tracks.
ER 46420 — L-Edit has been enhanced with a TCL interface for executing the C based UPI functions

Corrected Problems for L-Edit

DR 28269 — UPI functions are now available for guard ring generation.
DR 44003 — Windows style C: and Z: drives no longer appear in file browsers when browsing to Linux paths.
DR 44780 — Calibre highlighting in L-Edit and S-Edit now support “custom colors” from Calibre RVE. Other fixes in Calibre highlight colors.
DR 44940 — Nitro now allows the Top Cell name to be different than the Verilog module name.
DR 45485 — Fixed problem where OASIS file was incompletely imported.
DR 45493 — The duplicate, offset, and distribute horizontally operations now place electrical ports correctly.
DR 45570 — A custom script may now be added for Oasys.
DR 45589 — DEF is now imported correctly when DEF grid is different from L-Edit grid.
DR 45693 — The ability to map a specific parameter to another for the photonic extract netlist features has been added.
DR 45894 — Fixed problem where Japanese cell names were incorrectly decoded during a DXF import.

Enhancements for Library Manager

ER 44286 — The Libra