Cadence AWR 设计环境平台电子设计自动化 （EDA） 软件套件为射频/微波工程师提供了创新的高频电路、系统和电磁 （EM） 分析技术。当今的微波和射频工程师使用这个功能强大的开放平台来设计从基站到手机再到卫星通信的无线产品。AWR 设计环境软件的优势很简单：提供卓越用户体验 （UX） 的直观使用模型、提供速度和准确性的强大仿真技术，以及支持进出第三方工具的数据的开放式设计流程。
AWR Design Environment 25.10.010 | 978.0 mb
Cadence has released AWR Design Environment 25.1 ISR1. This platform provides RF/microwave engineers with integrated high-frequency circuit (Microwave Office), system (VSS), and EM (AXIEM/Analyst) simulation technologies and design automation to develop physically-realizable electronics ready for manufacturing.

AWR Design Environment V25.1 What's New

What's New Organization
The Cadence AWR Design Environment V25.1 What's New document is organized into several sections:
- AWR Design Environment Features - Common improvements to all products.
- Microwave Office Features - Cadence Microwave Office design-specific software improvements.
- Visual System Simulator (VSS) Features - Cadence Visual System Simulator (VSS) communications and radar systems design-specific software improvements.
- Virtuoso Studio RF Features - Virtuoso Studio RF-specific software improvements.
- Known Issues - Known issues in the current version.
- Migration Issues - Migration issues from previous versions to the current version.
- Version 25.1 ISR Updates - Updates for minor versions.
Major Features Overview
Limited Release Features
- The current release includes select "Limited Release" features. Cadence is releasing these features during development to request customer feedback on the feature's ability to solve a full range of engineering problems. To use these features please contact your local Cadence Sales representative for documentation and any necessary license(s). Cadence strongly encourages you to provide feedback to help determine that these features solve the intended engineering problems.
AWR Design Environment
- UI Themes: Customize the workspace with light or dark mode themes.
- High DPI Monitor Support: Sharper rendering of text and icons on 4K+ monitors.
- Python Support: Run Python scripts from within the AWR Design Environment platform.
- Updated Utilities: Cross-platform support for utilities under the Scripts menu.
- Options Grid Filtering: Find options faster using the Search bar.
- Customize Dialog Box Filtering: Find commands faster using the command category drop-down list.
- Measurement Dialog Box Improvements: Save mouse clicks with new buttons.
- Enhanced Status Window: Find operational messages faster using the Search bar.
Microwave Office
- Optimizer Improvements: New screener method that is suitable for designs with many variables.
- Layout Pin Names: A new pin connectivity model that supports greater complexity and is compatible with the Virtuoso® Studio model.
- Design Rule Check (DRC) Enhancements: A new DRC Errors window.
- Power Amp Design Flow in the AWR Design Environment: A power amplifier design application note.
- Create New Process Tool for Creation of PCB PDKs: A RAK describing how to create a PDK intended for PCB designs.
- Differential Filter Design: Application note on designing differential filters highlighting the MMCONV block and Common Mode Rejection Ratio.
Virtuoso Studio RF
- Virtuoso Design Link: Instantiate Cadence Virtuoso Studio designs into Virtuoso Studio RF software for advanced RF analysis.
- Silicon RF/mmWave IP Creation: Create Silicon IP utilizing Virtuoso PDKs in Virtuoso Studio RF software, and share the schematic and layout with Virtuoso Studio software.
- Spectre Interface: Easily set up Spectre Circuit Simulator simulation within Virtuoso Studio RF software.
- Pegasus/PVS Interface: Run Pegasus/Physical Verification System (PVS) DRC and review errors with an updated error viewer.
- EM Intergrations: Run EM and thermal simulations directly from the Virtuoso Studio RF environment.
Visual System Simulator (VSS)
- Distributed VSS Sweeps: Reduce RFI, RFB, and Time Domain simulation times with parallel simulations.
- Phased Locked Loop Design: Design and analyze a PLL using behavioral models.
- RF Communication Design: Set up RFB and RFI sims for cascaded Budget Analysis.
What's New in AWR Design Environment - Product Version 25.1 ISR1, August 2025The Cadence AWR Design Environment platform version 25.1 ISR1 software includes the following new features, enhancements, and user interface changes.
New Utilities
- The follow utilities are available under the Scripts menu:
- AMP_F File Generation: Creates a data file formatted for use with the AMP_F VSS amplifier element.
- Occupied Bandwidth: Measures the Occupied BW of a digitally modulated signal, which is a common digital modulation metric.
- Spur Finder: Identifies spurs in a spectrum.
Data Files
- The error message issued when attempting to parse a data file containing an invalid character now includes the line number where the error occurs, along with the column number and invalid character.
- Design Management/Version Control
- Restored the missing icons from LPFs under version control.
- A "VC" node now displays under the Circuit Symbols node in the Project Browser when connected to a source repository. Listed under the VC node are the symbol files in the repository, and listed under the file nodes are the symbols in the files.
- The Rename and Delete commands are now disabled for unlocked symbol files.
Extraction
- Schematic subcircuits are now extracted correctly in the z dimension when schematic Layout option Flipped Z is selected and an Offset is specified.
Layout
- Fixed issues with layout Boolean operations that include sh