Altair PollEx 2026 | 900.9 mb
The Altair development team is pleased to announce the availability of PollEx 2026 is a PCB-level Electronic Design Automation (EDA) software suite covering design review, analysis and manufacturing. Release Notes: PollEx 2026 SALIENT FEATURES
Adding and modifying new license features
• New license feature code: PollExMFG is added for the PollEx manufacturing options which will draw the same 30 AUs.
• Changed license feature code: PollEx UPE application is available in PollExBasic feature which will draw 10 AUs from 30AUs.
Adding Altair License Utility
• Altair License Utility is added in PollEx 2021.1 launcher.
Adding Altair License Management System setup panel
• The environment variable setting panel is added during install. This panel is only displayed if the environment variable has not been set.
Adding design data saving option in PollEx PCB
• Added a feature to save design data in a project directory with a compressed file (*.tgz) to share relevant data conveniently.
Added SI Explorer
• Added a feature to support pre-layout analysis SI Explorer menu. A feature to perform pre-layout analysis was added. PollEx SI Explorer menu allows to validate the design decisions throughout the design process including the selection of parts, add materials, construct board layer stack-up and create the net topology.
• Upon executing PollEx SI Explorer, the SI Explorer dialog comes up. You can start pre-layout signal integrity analysis from the scratch.
. Create layer stackup
. Create VIA model
. Create Transmission Line Model
. Create Net topology (Single-ended, Differential, Multi-coupled)
• Perform Signal Integrity Analysis (Waveform, Eye-diagram, Network Parameter)
Adding a feature to display S/Y/Z parameters
• Adding a feature to display S / Y / Z parameter in Network Parameter viewer, PollEx SI. By using this function, it is possible to compare and measure by opening the S / Y / Z parameters extracted from various conditions
Design and engineering require a system-level view of products and systems. The integrated design of mechanical behavior and electronics is a trademark of today’s product development. Based on a strong foundation of mechanical simulation software, Altair has expanded into areas of systems simulation and electromagnetics. Altair’s Pollex PCB solvers and verification tools extend these capabilities into a new domain, allowing Altair to provide software for system-level design decisions.
Altair PollEx is the most comprehensive and integrated set of PCB design viewing, analysis and verification tools in the market for electrical, electronics and manufacturing engineers. PollEx is an open solution, which transfers data flawlessly between different ECAD and simulation environments. While PCB design tools are traditionally reserved for PCB design engineers, engineers from other disciplines like hardware design, manufacturing, testing and mechanical need to also access, review and analyze the design and manufacturing data of PCBs and their Integrated Circuit (IC) packages.
PollEx provides unsurpassed connectivity to all relevant ECAD systems and formats as well to third party PCB simulation software and brings Design for Excellence (DfX) through a common application and a powerful set of rule-based design checks addressing post-design process constraints in the early design stages.
Its many features include query, measure, finding objects, and various reporting. PollEx operates in an open environment, which can transfer data flawlessly between different ECAD and simulation environments.
SALIENT FEATURES
Adding a feature to export layer images
- PollEx PCB supports to export images of Artwork layers and Physical layers. Supported formats are *.JPG and *.BMP formats. The feature can be used from the menu File – Export To – Image in PollEx PCB.
Adding a feature to support LPDDR4 analysis
- A function to analyze LPDDR4 added to the Automatic DDR Bus Analysis feature in PollEx SI. LPDDR4 timing standard table was added.
In the existing DDR technology, the Vref voltage, which is the measurement reference for timing data and address buses, was used as a fixed value, but the Vref voltage in LPDDR4 is generated inside the IC through the training process. If the Extract Vref_DQ using analysis result option is used, the Vref value is searched in the manner specified by JEDEC. As a result of analysis for all data/address buses of ICs, the voltage level at which the eye is the widest open is obtained, and the Vref value is determined by their middle values. If the Use user defined value option is used, user can set the required Vref value.
Replacing SI to HyperSpice Engine
- The Spice engine of PollEx SI has been changed to HyperSPICE from Polliwog Spice since only the Spice engine was changed internally with same user GUI. However, the default Spice Control Parameter is changed.
Adding a feature of impedance map
- A function to display the Impedance Map in the result of the Impedance check item of PollEx DFE+ was added. After performing the Impedance check upon clicking the Impedance Map button in the result table, the Impedance Map dialog is displayed. By using this menu, user can easily find the impedance mismatch area in the full path of the entire BUS.
Adding a feature of crosstalk coupling table mapping
- A function to display the Backward Crosstalk Coefficient(kb) Coupling Map in the result of the Crosstalk Noise check item of PollEx DFE+ was added. After performing the Crosstalk Noise check upon clicking the Coupling Map button in the result table, the Coupling Map dialog is displayed. By using this menu, user can easily find the areas where crosstalk is vulnerable in the full path of the entire BUS.
Adding a Power Integrity Check feature
- A function to check Power Integrity has been added to PollEx DFE+. The newly added functions are IR-Drop, Loop Inductance, and PDN Impedance.
- IR-Drop Check
IR drop refers to a voltage drop that appears at the resistance component of power network. IR drop is the electrical potential difference between power source and load component during a current flow. If the voltage level supplied to the component is lowered due to IR-Drop, the system malfunctions or the Rising/Falling time of the signal is delayed, causing a Signal Integrity problem. Therefore, in order for the component to work properly, it is necessary to check whether the amount of IR-Drop is within the limit value allowed by the component. This item checks whether the voltage level of the specified component is lower than the specified level.
- Loop Inductance Check
In PCB, the power line generally refers to a power network that connects the power source(VRM) and the load components. The characteristics of these power trace configurations can be determined by the power delivery network (PDN) of the PCB. PDN operates like a passive component such as a coil or capacitor, depending on its physical properties. Resonance occurs due to these passive components, and the current flowing through the resonance structure causes signal distortion and EMI problems. PDN impedance should be designed as low as possible. Usually, in order to make the PDN impedance low, a decoupling capacitor is installed around the power pin. For this decoupling capacitor to work effectively, the loop inductance between the power pin and the decoupling capacitor must be designed to be small. This item checks whether the loop inductance between the power pin and the decoupling capacitor exceeds the value specified by the user.
- PDN Impedance Check
In PCB, the power line generally refers to a power network that connects the power source(VRM) and the load components. The characteristics of these power trace configurations can be determined by the power delivery network (PDN) of the PCB. PDN operates like a passive component such as a coil or capacitor, depending on its physical properties. Resonance occurs due to these passive components, and the current flowing through the resonance structure causes signal distortion and EMI problems. Therefore, precise analysis of PDN Impedance is very important in the design phase. This item checks whether the PDN impedance of the specified Power Pins are higher than the target impedance specified by the user.
Adding a feature to export thermal results
- In PollEx Thermal, a function to output the thermal analysis result in standard file format was added. Analysis results can be output in Excel format or .CSV format. At the Thermal Analysis Dialog, using File/Export to CSV menu, user can generate result file. Among the analysis results, the PCB Top/Bottom surface temperature is saved as designname_Top/Bottom.xlsx file, the saved format is the X,Y coordinates and temperature values, the component temperature is saved as the designname_Component.xlsx file, and the saved format is the Reference Name , PlaceLayer, X/Y coordinates, and temperature values.
PollEx is the most comprehensive and integrated set of PCB design viewing, analysis, and verification tools for electrical, electronics, and manufacturing engineers. PollEx transfers data flawlessly between the industry’s most popular ECAD and simulation tools and enables many of the world’s major electronics corporations to quickly visualize and review PCB designs. Its checking tools detect issues early in the design to avoid product failures and simplify manufacture and assembly. PollEx 2021 is available with a long list of new features, corrections, and improvements. Samsung SDI Improves PCB Development with Altair PollEx Altair is a global technology company that provides software and cloud solutions in the areas of product development, high performance computing (HPC) and data analytics. Altair enables organizations across broad industry segments to compete more effectively in a connected world while creating a more sustainable future. Product: Altair PollExVersion: 2026Supported Architectures: x64Website Home Page : www.altair.com
Language: multilanguageSystem Requirements: PC *Size: 900.0 mb购买后，将显示帖子中所有出售内容。
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