Cadence Virtuoso Studio IC25.10.000 | 13.2 Gb
Cadence Design Systems, Inc. announced the new Cadence Virtuoso Studio IC25.1 ISR6 (25.10.060), a next-generation design platform for custom analogue designs that allows more than a 3X improvement in design throughput, enabling customers to meet aggressive time-to-market goals. Virtuoso Studio IC25.1 Overview
Leveraging over 30 years of industry experience, Virtuoso Studio IC25.1 provides broader support for RF, photonics, mixed-signal, and advanced heterogeneous designs. The new AI-powered Virtuoso Studio advances productivity via automation and innovative features, reimagined infrastructure and new levels of integration that stretch beyond classic design boundaries.
Virtuoso Studio RF
Virtuoso Studio RF empowers designers with a platform tailored to RF-specific requirements while leveraging Cadence design, analysis, and manufacturing technologies. This cutting-edge RF design platform offers a tightly integrated environment for schematic capture, layout, simulation, and in-design analysis. Virtuoso Studio RF environment enables engineers to develop high-performance designs across RF silicon and laminate technologies from concept through validation—all without switching tools. By unifying these capabilities, Virtuoso Studio RF improves accuracy and accelerates design cycles, ensuring efficient RF system development. Cadence Virtuoso Studio, Release Version IC25.1 ISR6 - Date: June 2026
CCRs Fixed in Virtuoso Studio IC25.1 ISR6 3342507 ALM placement with Apply Group enabled generates incorrect device orientation
3341578 Correct chaining behavior when 'Chain' is selected during Generate Selected From Source
3340554 Virtuoso Studio exits unexpectedly after deleting wires and vias on a design containing bus constraints
3339897 Last few iterations of Monte Carlo simulation fail to evaluate expressions
3339248 Delete Overlay, WSP, Routing & Trim button is deleting APR_OD_global and APR_PO_global WSP
3339200 Pins are getting moved from their location
3339049 Device set as a probe in the hbstb analysis is not mapping to the DSPF
3337003 xmelab error when editing a textual behavioral view
3336107 DSPF-to-ADE fails to map some net names two levels down the hierarchy
3336057 Clicking Apply in the Array Assistant creation flow leaves the sandbox unsynchronized, causing subsequent Modgen issues
3335675 Virtuoso Studio exits unexpectedly with ADE Verifier
3335606 In IC25.1, Virtuoso Studio exits unexpectedly during migration using Compound Pattern Engine
3335275 UVM_TESTNAME does not update per point when using VAR in sweep or corner
3333191 Auto Via stops responding for large diagonal via
3332867 Resistor placement is different when compared to the golden layout, which has six rows
3332649 Die alignment changes stack order and rotation during alignment
3332214 Unable to adjust vertical spacing between PMOS and NMOS devices
3331488 Netlist Log in View Log Messages is disabled where the point netlisting during simulation flow created the point netlist
3331099 Monte Carlo points are reported as simulation errors even though the simulation completes successfully
3330554 Netlist fails when using VAR for UVM_TESTNAME
3330035 Device area calculation failure for top-level schematic
3329943 During layout migration, transparent routing cells are not flattened when flattenRouteCells is set to t
3329851 Provide a method to inject pre-simulation commands into the runSimulation script
3329844 The Add Probe command does not follow the probeHiliteLppList order
3328586 Enhance the error message when calcVal is used in the optimizer run mode
3328264 Provide an environment variable to control bindToOpen enablement below the I-DSPF cellviews
3327415 Die alignment fails with incorrect window warning and invalid argument error
3327354 LSCS does not work correctly with point netlisting and third-party simulators
3327150 The MAPI process does not provide detailed compilation information for text cellviews
3326548 Netlisting error on missing SNAP netlist when running a run plan history
3326442 Delete All Markers does not save lower-level cellviews
3326332 After running the Delete All Markers command, the lower cell views are not checked in and remain checked out
3325959 Aging testcase with Run Plan fails for different corner in every rerun
3325181 Virtuoso Studio exits unexpectedly
3324458 Auto Via creates diagonal via in DRC violated scenario
3323163 Legend check box cannot be deselected in the Save Image form when Legend Position=Inside in the Graph Properties form
3322279 Automated placement and routing leaves open nets because of a failure in insertion of a via between different layers
3322257 Deleted markers not saved in the edited cellview when using the Modified Cell View Auto Save option
3322154 S-Parameter Assistant is not plotting S-Parameter data
3321936 Virtuoso Studio exits unexpectedly when working with PSFXL
3321756 calcVal cannot resolve values for more than 999 points when a history is referenced
3321609 Schematic Find does not reset the searched values after turning off the Match Master Properties option
3320562 EM configuration fields do not function properly in the View Stackup for package-only models
3319970 Check mark of 'Max. Iterations' in Design Optimization Options form is not useful
3319224 Auto Via drops vias for testcases with minDiagonalSpacing violations
3319009 Bad target-created WSPs prevent successful migration
3318808 Taskbar title uses _NET_WM_NAME when _NET_WM_ICON_NAME is empty
3318213 Incorrect maeDesignPoint and maeCorner information in runObjFile in the PSF directory
3317756 EMIR simulation stops responding after design netlisting when IDSPF config sweeps are set up
3316771 Virtuoso Studio IC25.1 is running slow
3316566 Error is observed when updating NFET and PFET devices to include maxDeviceVoltage
3316120 Virtuoso Studio exits unexpectedly when sending model parameters to Virtuoso Visualization and Analysis XL Table
3315946 Virtuoso Studio IC25.1 ISR4 exits unexpectedly when probing Calibre LVS report nets
3315440 Remove Configuration file does not have the required path format from schMapLoadConfig message
3315395 Auto Cluster assistant creates incorrect clusters when 'Range' is set to 'Full'
3315377 Auto clustering fails when 'Range' is set to 'Visible'
3314558 Temperature sweep fails in AMS simulation
3312734 The option outputallharms=yes from the Envelope analysis settings is not included in the corner netlist
3311730 Design variable 'temperature' is automatically set with Virtuoso Multi-Process
3311255 emirreport exits unexpectedly with no errors in the log file
3311237 NetSet attributes are not preserved for hierarchy supply connections with unlPortDrill
3308993 Tolerance specs are being incorrectly translated into FMC goals
3308972 The dspf_include statement is netlisted twice for a single DSPF file with blackbox, resulting in Spectre error
3308158 Virtuoso ADE Assembler stops responding, and outputs are shown in Evaluating state even after the simulation completes
3308042 cdsPerfDiag callstack timeout cannot be configured in non-graph mode
3308016 Results view remains empty during and after a simulation run when the 'Hide All Tests' option is selected
3307927 Application window title is not displayed when _NET_WM_ICON_NAME is not set
3306935 Inactive reliability setup incorrectly adds an incomplete include .scs statement in the netlist
3306270 No isolation attributes extracted for a specific port when certain SKILL variables are enabled in Virtuoso Power Manager
3305761 Device area calculation fails when pPar parameter value is used
3305076 Annotation does not work with Virtuoso Multi-Process
3304645 AMSD: Temperature sweep in Corner setup runs all simulations at first sweep value in AMS simulations
3303643 cphSbDefineSoftBlock returns nil when validLayers are defined using LPP
3303361 Assisted Import creates viaDef that is absent during enablement
3303176 Virtuoso ADE Assembler stops responding after netlisting completes
3303010 Stretching wire segments connected to a solder dot causes disconnects based on based on stretch direction of the wire
3302778 Multi-Test Editor cannot save the updated values of design variables correctly
3302735 The flight line color does not update when probing the net in the schematic after display packet information is updated
3302588 Netlist modified by Simulation Monitor should not evaluate dependent expressions in parameters
3302028 Simulation errors when running multiple reliability analyses across multiple runs
3301757 Layout migration exits for complex bound devices in instances with Transparent and Forced Descend enabled
3301157 awvPlaceYMarker not placing the marker on the correct waveform strip
3299407 Re-evaluation of calcVal expressions fails; successful only when simulation is run
3298944 VAR-based vector substitution not applied during netlisting, leaving vec_include fixed to first file
3298084 Apply Placement with 'Init Layout' off takes excessive time
3297373 Output mapping is missing when running DSPF2ADE Corner Sweeps with AMS Designer
3297100 minNumCut set by shield constraint is not applied by advanced tie shield
3296717 SFE-874 error displayed when using variables in genNameMapDB.scs
3296661 Corner model group fails with VAR-based DSPF and model sweeps in the DSPF-to-ADE flow
3296574 Error ADE-5036 displayed when opening results in ADE Explorer or ADE Assembler
3296076 The netlister does not report an error when there is a pin mismatch between the schematic and the symbol
3295699 Virtuoso Studio exits unexpectedly when using Turbo Bus
3292913 An error occurs while performing capture and replay tasks
3292256 In IC25.1 ISR3, the Move command in Virtuoso Studio Layout XL takes excessive time if row region exists
3291494 Create Footprint: Bus signals not routed correctly in abstract schematic
3289101 Device-level router does not route all possible open nets for the first run
3286364 acosh returns negative real component for the complex inputs with negative imaginary component
3286144 In LSCS mode, Job Log and Netlist Log options are inactive even when logs are available
3285887 Custom pattern from Modgen template is not applied to APR constraint step
3285886 Device area calculation fails when pPar parameters are used in a cell
3284754 Net tracer does not trace across die stack in silicon stack with ITDB
3283683 Noise Summary Report window remains empty when sweeping string type variable
3282128 lef2oa/oa2lef support for ARRAYSPACING ARRAYWIDTH needs to adjust the value for LEF/OA semantic difference
3280543 Application window title is not displayed in the taskbar
3280293 Metal orientation set by viaConfig does not work during device-level automated placement and routing
3274295 Create Auto Via does not create vias correctly for butting blockages
3273152 Variable evaluation is different when using the point netlisting flow
3272061 AMS simulation with a pure analog netlist runs much slower than a VAMS netlist
3271878 Variables grouped as parametric sets are not highlighted on Rocky Linux version 8.10
3271007 Support Hierarchical Current Probing in AMS simulation
3270278 leSearchHierarchy returns incorrect results when two instances of the same master are placed with overlap
3264615 EMIR simulation not binding an instance to I-DSPF view when HED configuration sets its binding to schematic
3254450 Unevaluated VAR expressions are printed in genNameMapDB.scs
3251920 Virtuoso Studio stops responding when running the Calculating Area and Density command on layout
3249648 UNL parameter and port name conflict remains unresolved
3247142 Virtuoso Multi-Technology Solution: Export Design flow reports unsupported instances of OSM and BSM components
3245562 Virtuoso Space-based Router creates unnecessary jogs when connecting to pins
3241987 Capture and Replay command created in IC23.1 does not work in IC25.1 and displays 'Replay file version mismatch' error
3237373 Redundant patch shapes remain after standard cell automated placement and routing is run
3235734 DSPF probe translation fails for current signal
3232110 Performance issue in stress and aging simulations during reliability analysis
3206495 Hierarchical oaScan did not work correctly for switch masters on schematic hierarchy
3204067 Incorrect simulating status reported for failed Monte Carlo points in LSCS Mode
3198006 Source PSF directory from 'Move Data' operation is not deleted
3183721 Transmission line model generation may incorrectly report a failure due to NFS synchronization delays
3146578 leSearchHierarchy does not work as expected
3132533 Results directory for Monte Carlo simulation is missing when using LSCS with a third-party simulator
3120498 Voltus-XFi reports the simulation as successful despite a segmentation fault in Spectre
3081841 Generate EMIR Configuration is misleading as it suggests that the emir.conf file is being recreated
3057135 Add information and logs about netlist errors in Voltus-XFi
3045325 Assisted Export in Virtuoso Multi-Technology Solution reports unsupported rotated die pad instances
3020509 Via array is deleted when changing row and column using the Edit Via Properties form
2763184 Auto Checkout and Auto Checkin preferences forms ignore previously applied settings
2684434 No warning is displayed when the schematic pin count exceeds the corresponding symbol pin count
2657483 leSearchHierarchy returns incorrect results when two instances of same master are placed with overlap
2462645 cdsfrb_lsf incorrectly defines variables with empty value
2349002 Virtuoso Studio exits unexpectedly while searching for text in the simulation log
1949720 leSearchHierarchy does not work as expected
June 2026
Cadence Virtuoso Studio leverages 30 years of industry knowledge and leadership in custom/analog design to give you broader support for systems, including RF, mixed-signal, photonics, and advanced heterogeneous designs. Innovative artificial intelligence (AI) techniques, cloud enablement, infrastructure improvements, and integration across Cadence products complement these design flows, creating a hub for efficiently delivering real designs for the real world. Virtuoso Studio: Custom Design for the Real World The analog design world we know is evolving. And so is Virtuoso technology. Learn how the best analog tools just got better to help you keep pace with your challenging design issues. The AI-powered Virtuoso Studio custom design solution provides innovative features, reimagined infrastructure for unrivaled productivity, and new levels of integration that stretch beyond classic design boundaries.Cadence is a pivotal leader in electronic systems design, building upon more than 30 years of computational software expertise. The company applies its underlying Intelligent System Design strategy to deliver software, hardware and IP that turn design concepts into reality. Cadence customers are the world’s most innovative companies, delivering extraordinary electronic products from chips to boards to complete systems for the most dynamic market applications, including hyperscale computing, 5G communications, automotive, mobile, aerospace, consumer, industrial and healthcare.Сopyright holder \ Distributor: Cadence Design Systems, Inc.Product Name: Virtuoso StudioVersion: IC25.1 ISR6 (25.10.060) *Supported Architectures: x86_64Website Home Page : www.cadence.comLanguages Supported: englishSystem Requirements: Linux **Size in archive: 12.7 GbRecovery information: 3% archive & 2.rev file * System Requirements:
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