Active-HDL™是基于Windows®的集成FPGA设计创建和仿真解决方案，用于基于团队的环境。Active-HDL的集成设计环境（IDE）包括完整的HDL和图形设计工具套件以及RTL /门级混合语言模拟器，用于快速部署和验证FPGA设计。 Active-HDL的集成设计环境（IDE）包括一个完整的HDL和图形设计工具套件以及用于快速部署和验证FPGA设计的RTL /门级混合语言模拟器。设计流程管理器在设计输入，仿真，综合和实现流程中唤起120多种EDA和FPGA工具，并允许团队在整个FPGA开发过程中保持在一个通用平台内。 Active-HDL 10.1提供了许多新功能和增强功能，可简化基于团队的设计，提高设计效率，以及VHDL，Verilog®，SystemC™，SystemVerilog和EDIF项目的行为，RTL和时序仿真速度。新版本采用独立于FPGA供应商的版本，支持所有领先的C / HDL综合和实现工具，可直接从Active-HDL环境启动。安装程序自动安装所有系统库，并允许选择运行HDL仿真所需的目标FPGA技术和供应商特定库。本次带来破解版下载，含破解文件，有需要的朋友不要错过了!设计流程管理器在设计输入，仿真，综合和实现流程中调用200多种EDA和FPGA工具，并允许团队在整个FPGA开发过程中停留在一个通用平台内。Active-HDL支持来自英特尔®，Lattice®，Microsemi™（Actel），Quicklogic®，Xilinx®等行业领先的FPGA器件。 Aldec, Inc., a pioneer in mixed HDL language simulation and hardware-assisted verification for FPGA and ASIC designs, advances VHDL’s verification capabilities with Active-HDL, version 13.0. This latest release introduces support for VHDL-2019 protected types with generics, composites of protected types, pointers to objects of protected types and composition with protected types.Protected types were introduced in VHDL-2000 to allow the creation of class-like objects (similar to classes in C++), which then later became required for shared variables in VHDL-2002. In VHDL-2019, the capabilities of protected types have been significantly improved to address new use models essential for the creation of complex testbenches that require advanced data structures. Protected types are a powerful mechanism for creating functional coverage, random test generation, messaging, unified error reporting and verification data structures such as memory models, FIFOs and scoreboards. Engineers can also use protected types on an entity interface for sharing a single memory among multiple AXI4 memory-mapped external peripherals, ideal for verifying SoC FPGAs used for multi-sensor data aggregation. What's New in Version 13
The following is a brief overview of new features and changes introduced to Active-HDL 13 (BUILD 375.8320, 3/18/2022). Performance Improvements
- The randomization performance has been enhanced for specific cases of random constraints.
- Opening and closing time of Active-HDL projects containing a large number of objects has been significantly reduced.
- The time required to change an active library in a design containing a large number of files has been significantly reduced.
- Performance of updating the design contents by using the Refresh contents dialog box has been significantly improved.
- The compilation time of logical and arithmetic constructs utilizing a number of operands has been reduced.
- The time of compilation of VHDL source files in the batch mode (VSimSA) has been significantly decreased. Compiler and Simulator
NOTE: Due to internal changes in the compiler and simulator as well as updates in third-party tool libraries, all user-defined libraries should be re-compiled after the installation of Active-HDL 13. The installation program of the current version delivers and installs only the updated system and vendor-specific libraries that do not require re-compilation after Active-HDL is installed. All existing designs will not have any problems associated with re-compiling the libraries. If you update Active-HDL to version 13 and do not re-compile your design libraries, the following error message will be displayed in the Console window:
# ELBREAD: Warning: Files created by the old version of the compiler found.
# ELBREAD: Error: Library '<library_name>' has incompatible format. Recompile all library units.
VHDL Compilation and Simulation
- Starting from Active-HDL 13, compilation of constructs specific to the IEEE Std 1076-1987 standard is allowed only in the compiler modes compliant with IEEE Std 1076-1993 and IEEE Std 1076-2002. If required, it can be turned off by passing the -disable87 argument of the acom command. In the remaining compiler modes, that is, VHDL 2008 and VHDL 2019, the compiler does not accept the constructs of IEEE Std 1076-1987 and reports an error. Note also that the corresponding changes are implemented in the graphical user interface. For more information on these changes, refer to the User Interface section. (SPT80277)
- The COMP96_0283 error message provides information about the type of an object triggering the message and incorrect number of indices specified by the user. (SPT80653)The following features introduced by IEEE Std 1076-2019 standard have been implemented to the current version of the compiler and simulator. In order to use them, if not stated otherwise, they must be enabled with the Standard version option in the Compilation | VHDL category of the Design Settings dialog box or by using the -2019 argument of the acom command:
- VHDL 2019 lowers the precedence of the ** exponentiation operator below the abs and not unary operators. In the previous standard revision, all these operators had the equal precedence.
- The arrays and records of the file type are supported. All elements of such composite types must be of the file type or the composite type consisting only of subelements of the file types.
- The sequential block statements have been introduced. They allow grouping sequential statements in the same way as concurrent statements are grouped by the regular block statements. A sequential block statement can contain any sequential statement. In particular, other sequential block statements can be used there. The statements within a block can be preceded by declarations of objects which are local to the block. They are not visible outside of it and are removed from memory after the block execution is completed:主要功能和优点 项目管理
可配置的FPGA / EDA Flow Manager与200多家供应商工具接口，使团队可以在整个FPGA开发过程中保持在一个平台上
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Product: Aldec Active-HDLVersion: 13.0.375.8320Supported Architectures: x64Website Home Page : www.aldec.comLanguages Supported: englishSystem Requirements: Windows *Size: 577.5 mb