Cadence XCELIUM version 23 | 8.6 Gb
Cadence Design Systems, Inc. , the leader in global electronic design innovation, is pleased to announce the availability of XCELIUM 23(XCELIUMMAIN) is part of the Cadence Verification Suite and supports the company’s Intelligent System Design strategy, enabling pervasive intelligence and faster design closure.
Defects fixed in XCELIUM23 =============================================
CCRID Product Title
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AVSREQ-127683 | JUPITER_BRIDGE | Jupiter simulation failure (was ~4x sim slow down)
AVSREQ-127594 | XPROPAGATION_GENERAL | xmvlog_cg: *E, NOTPAR with both xprop enabled and -access +rwc
AVSREQ-126960 | SIM_VHDL | Internal exception when calling finish with DPI present in environment
AVSREQ-126633 | LP_1801 | Use of * does not work with -isolation_signal
AVSREQ-126487 | MSIE_ELAB | Xcelium 20.07 AGILE crash in Assertion
AVSREQ-126165 | SPECMAN_E | OTF GC during string match causing wrong results
AVSREQ-126077 | SIM_SV | sv_seghandler coming from sv stream
AVSREQ-125037 | XPROPAGATION_GENERAL | X-Propagation Disabled for No if and no case in VHDL
AVSREQ-124836 | DMS_ELAB | Need to resolve amsspice warning about multiple -libmap and multiple -top, incorrect bindings since the provided libmap
AVSREQ-124817 | DMS_LP_AMS | LP AMS Elaboration Crash
AVSREQ-124765 | SV_CLASSES | Typed contructor Elab changes
AVSREQ-124708 | GLS_GENERAL | The number of UDP inputs allowed exceeds current maximum limit (15) . Is there any workaround possible for error UDPNIN?
AVSREQ-124687 | JUPITER_COMPILER | portbus with width greater than 2000 causing increase in elaboration time and memory
AVSREQ-124631 | SV_PERFORMANCE | xmelab performance - after cu_optimize::cu_zoptimize
AVSREQ-124597 | SPECMAN_INTEF | Driving list of bit port fails
AVSREQ-124582 | DEBUG_DESIGN_DATABASE | lwdgen performance issue - nested forgen
AVSREQ-124342 | XRUN_GENERAL | Option -autofetch is not properly managed along with other options
AVSREQ-124059 | LP_1801 | remove lps_enable_merge_ho_split from NEWPERF
AVSREQ-123828 | PROFILER_SIM_MEMORY | fanout information for expanded nets
AVSREQ-123765 | VPI_GENERAL | SYSTF INVHIER when passing hierarchy that includes space to -xmhierarchy
AVSREQ-123648 | LP_1801 | when lps_infer_upf_supply is used MULSPLY is not created when there are conflicting drivers
AVSREQ-123639 | DESIGN_DATABASE | Investigate: Parameter displayed as -1 instead of actual value in LWD - correct in Snapshot
AVSREQ-123592 | COVERAGE_ALL_COVERAGES | vManager Client crashes when trying to rank session runs including Formal runs - root cause is not clear
AVSREQ-123516 | DMS_LP_AMS | XMSIM internal error MESSAGE: ams_pwr_net2dms_enable
AVSREQ-123515 | SPECMAN_INTEF | Runtime error at method_port invocation from SV class instance
AVSREQ-123490 | UVM_SV | uvm_re_match returns wrong match result
AVSREQ-123442 | DEBUG_DESIGN_DATABASE | waveform annotation and power browser infromation for isolated modport signal is incorrect
AVSREQ-123339 | RAND_SOLVER | xmsim: *F,RNDUNR: XCELIGEN assertion failed - elem->is_field()
AVSREQ-123328 | JUPITER_SOUTH | internal error in South *F,MCEASRT
AVSREQ-123302 | FUNC_SAFETY_CONCURRENT | MESSAGE: sv_seghandler - trapno -1 addr((nil))
AVSREQ-123221 | GLS_GENERAL | Xcelium build crash "Illegal writer – cag_get_driving_expr" (xmelab)
AVSREQ-123174 | SIM_SV | xmsim *F sv_seghandler
AVSREQ-123158 | DEBUG_DESIGN_DATABASE | Indago does not support showing isolation rules on interface signals
AVSREQ-123149 | SV_GENERAL | -ii_write doesn't work for NBAs in packed MDAs - further enhancement
AVSREQ-123144 | LP_1801 | RD; Use dot as a hierarchy separator for generate blocks in 'find_objects'
AVSREQ-123143 | ELAB_BIND | Using verilog compiled configuration in vhdl: BILCNF-error when using makelib/endlib
AVSREQ-123116 | LP_1801 | update XRIO upf file to include location self
AVSREQ-123075 | ELAB_SV_VHDL | Allow writing of mixed OOMR (from SV terminating in VHDL) support for additional VHDL datatypes (integer, real, arrays of above)
AVSREQ-123062 | CORE_RAND | Randomization clone not reproducing the contradiction message
AVSREQ-122958 | JUPITER_ENGINE | Support the -delay_udp_xminitialize option when Jupiter supports xminitialize of state variables.
AVSREQ-122858 | SV_INTERFACE | getting xmelab internal exception during ixcom compilation flow
AVSREQ-122857 | SPECMAN_INTEF | var_opt_core optimization causes a Specman warning: DEPR_VERILOG_WIRE_UNDEFINED
AVSREQ-122852 | COVERAGE_ALL_COVERAGES | Elaboration of VHDL with Generics issues Error *E,GENXCOV
AVSREQ-122787 | UVM_SV | uvm_re_match has different behavior when string order is different
AVSREQ-122762 | JUPITER_ENGINE | Add Multi-core support for -force_sequdp_xminitialize
AVSREQ-122722 | JUPITER_COMPILER | Fix the can_apply_ff_sens for x_latch_out
AVSREQ-122721 | JUPITER_SOUTH | Improve calc_ff_sens_index to distinguish between ranks of clk temperature
AVSREQ-122658 | CORE_RAND | False warning *W,RNDFUNAC when static variables are in functions
AVSREQ-122612 | MSIE_ELAB | Unexpected VIFUCOM not in 20.05.v002
AVSREQ-122611 | MSIE_ELAB | CUVUNF for out of primary function call
AVSREQ-122610 | MSIE_ELAB | CUVUNF for bind module in MSIE
AVSREQ-122609 | MSIE_ELAB | CNOIFC error not in 20.05.v002
AVSREQ-122509 | LP_1801 | Spurious SVINMP for interface in bind
AVSREQ-122507 | GLS_GENERAL | GLS: support DU names size more than 1023 character
AVSREQ-122505 | LP_1801 | Spurious LIBNOCON for internal power of liberty inside another liberty
AVSREQ-122471 | DMS_MSIE | Partitioner does not discard partition which leads to MSIE real to unreal boundary port connection error INCUSC
AVSREQ-122441 | ASSERTION_SVA | Misleading errors for procedural concurrent assertion
AVSREQ-122404 | SV_PERFORMANCE | NOTPAR error at elaboration
AVSREQ-122374 | SV_CLASSES | Unexplained ITPREF error
AVSREQ-122305 | PARSE_SV | Xcelium giving build error when SVA sequence is named "followed_by"
AVSREQ-122108 | MSIE_PERFORMANCE | redundant pak files are created and being read in bbox flow
AVSREQ-122105 | ELAB_SV | CLONE - Elaboration Error (INTERR)
AVSREQ-122104 | MSIE_ELAB | xmelab error: *E,VIFUCOM - incremental snapshot
AVSREQ-122026 | LP_1801 | The always block does not execute inside a power aware model.
AVSREQ-122020 | LP_1801 | Elements in Tcl list for isolation are not being processed
AVSREQ-121980 | SV_CODEGEN | xmvlog_cg crashing for user defined system task function call
AVSREQ-121962 | SV_INTERFACE | Tool Crash(INTERR) during Elaboration - cu_vifc_verify_lpvi_msie_combination
AVSREQ-121958 | DMS_LP_AMS | UPF VCT is not mapping real value for UPF Voltage from UDN VDD net to UPF supply_net in 20.03-v
AVSREQ-121834 | PROFILER_SIM_RUNTIME | -profile ,-prof_dump options does not work for a hang simulation
AVSREQ-121827 | LP_SIM_PERF | xmelab INTERR : cu_vifc_check_access - unmark flags mismatched
AVSREQ-121813 | PARSE_SV | xmvlog crash with message "apx - can't abstract pointer"
AVSREQ-121667 | ELAB_SV | Elaboration crash when bringing up Modem environment with Xcelium
AVSREQ-121642 | RAND_SOLVER | TRAT Ignored constraint (wrong solved results)
AVSREQ-121635 | LP_1801 | xmelab Internal Error in Low Power
AVSREQ-121538 | ELAB_SV | xmelab CRASH with $error( $psprintf("%d ",$time) );
AVSREQ-121529 | RAND_DEBUG | -xceligen oc_format=1 doesn't work
AVSREQ-121324 | CORE_RAND | Could not impose constraints on protected int queue: Internal error
AVSREQ-121306 | LP_1801 | MULSPLY highlights a bug in incorrect PG connection
AVSREQ-121280 | DEBUG_DESIGN_DATABASE | Source Code for scopes are not displayed in MSIE LWD
AVSREQ-121186 | MCE_XTIMATE | -mce_acc_estimation not allowing to complete simulation. Gives ZD loop warning.
AVSREQ-121057 | RAND_SOLVER | TRAT seems to drop constraint and cause contradiction
AVSREQ-120974 | RAND_SOLVER | Solver generates incorrect value in TRAT mode for implication constraints
AVSREQ-120947 | SV_CODEGEN | E,DLNORD with successful compile
AVSREQ-120896 | MSIE_ELAB | xmelab crash with cuabv_cmp_asrt_details_by_pibid
AVSREQ-120806 | MSIE_ELAB | Internal error with MSIE xmelab: *F,INTERR: INTERNAL EXCEPTION
AVSREQ-120756 | CORE_RAND | Solver timeout on foreach loop in constraint
AVSREQ-120677 | JUPITER_ARCHITECTURE | supply nets causing NACCed items
AVSREQ-120675 | JUPITER_BRIDGE | Continuous assignment delays on combinational cells being NACCed
AVSREQ-120659 | RAND_GENERAL | Randomization fails without information, doesn't generate tc clone
AVSREQ-120658 | DMS_MSIE | Primary recompilation while using MSIE single step flow
AVSREQ-120651 | SV_INTERFACE | Primary elaboration crash with UPF
AVSREQ-120648 | DMS_VLOG | SVRNM: Support for $value$plusargs statement in a resolution function
AVSREQ-120606 | SV_CODEGEN | INTERR MESSAGE: gq_st_gen_swbabp - class default
AVSREQ-120530 | XPROPAGATION_PERFORMANCE | Performance issue with 20.05 non-blocking assignment
AVSREQ-120525 | RAND_SOLVER | Tool Crash during simulation when TRAT - solver enabled
AVSREQ-120514 | RAND_PERFORMANCE | Randomization stuck with MOD operator
AVSREQ-120489 | DMS_MSIE | Replicated Top + Spice OOMR is generating CUVTNH errors
AVSREQ-120483 | ASSERTION_SVA | property wrongly activated when ##PARAM
AVSREQ-120363 | SV_PERFORMANCE | Optimization breaking functionality in a fork block
AVSREQ-120321 | DEBUG_DESIGN_DATABASE | Enum signal is incorrectly text-ref annotated with localparam value of same name
AVSREQ-120306 | MSIE_ELAB | Elaboration crash while making an incremental snapshot of DSS
AVSREQ-120279 | JUPITER_RTL_SC | simulation failure with Jupiter early access w464
AVSREQ-120181 | MULTI_CORE_ENGINE | simdiff : start_time end_time not working correctly
AVSREQ-120172 | MSIE_ELAB | Support number of partitions control in automsie flow
AVSREQ-120159 | VHDL_PERFORMANCE | simulator locks when probing at time 0.
AVSREQ-120150 | DMS_SVAMS | New SVAMS Parser (-svams_2019) nullifies the effect of -honorvams
AVSREQ-120110 | DMS_WREAL | *E CICINT error when mapping scalar net type in concatenation
AVSREQ-120071 | DMS_LP_AMS | 20.05.a001 MESSAGE: ams_pwr_net2dms_enable xmsim: *F,INTERR: INTERNAL EXCEPTION
AVSREQ-120070 | COVERAGE_CODE | specialize_if_type_has_covergroup incorrectly uses wrong type for instances with different type parameters used
AVSREQ-120064 | DMS_MSIE | Coercion fails with Auto MSIE
AVSREQ-120054 | COVERAGE_ALL_COVERAGES | xcelium coverage command generates *E,GENXCOV for vhdl-2008 generate
AVSREQ-120039 | SIM_PERFORMANCE | Debugging profile entry ENABLE(n), tail, rtn (method)
AVSREQ-119988 | PARSE_SV | xmelab error with NOTPAR
AVSREQ-119966 | LP_1801 | Signal tied to '0 not corrupted correctly during shutoff
AVSREQ-119960 | MSIE_ELAB | LWD support in MSIE bbox flow for Indago
AVSREQ-119959 | XPROPAGATION_GENERAL | X-prop distinct warnings for XFOVRD with same mode and different
AVSREQ-119951 | CORE_RAND | Random stability lost when adding breakpoint or reset
AVSREQ-119948 | LP_1801 | Signal tied to 0 does not get propagated at power up
AVSREQ-119897 | MSIE_ELAB | xmelab error: *E,VIFUCOM when running using EHF 20.06.e436
AVSREQ-119888 | VPI_GENERAL | setting vc call back on indexes changing specific indexes: all cb methods are called
Cadence's Xcelium Logic Simulation provides best-in-class core engine performance for SystemVerilog, VHDL, mixed-signal, low power, and x-propagation. It supports both single-core and multi-core simulation, incremental and parallel build, and save/restart with dynamic test reload. The Xcelium Logic Simulator has been deployed by a majority of top semiconductor companies, and a majority of top companies in the hyperscale, automotive and consumer electronics segments. Using computational software and a proprietary machine learning technology that directly interfaces to the simulation kernel, Xcelium learns iteratively over an entire simulation regression. It analyzes patterns hidden in the verification environment and guides the Xcelium randomization kernel on subsequent regression runs to achieve matching coverage with reduced simulation cycles. Xcelium is part of the Cadence Verification Suite and supports the company’s Intelligent System Design strategy, enabling pervasive intelligence and faster design closure.
Cadence's Xcelium Logic Simulation provides best-in-class core engine performance for SystemVerilog, VHDL, mixed-signal, low power, and x-propagation. It supports both single-core and multi-core simulation, incremental and parallel build, and save/restart with dynamic test reload. The Xcelium Logic Simulator has been deployed by a majority of top semiconductor companies, and a majority of top companies in the hyperscale, automotive and consumer electronics segments. Using computational software and a proprietary machine learning technology that directly interfaces to the simulation kernel, Xcelium learns iteratively over an entire simulation regression. It analyzes patterns hidden in the verification environment and guides the Xcelium randomization kernel on subsequent regression runs to achieve matching coverage with reduced simulation cycles. Xcelium is part of the Cadence Verification Suite and supports the company’s Intelligent System Design strategy, enabling pervasive intelligence and faster design closure.Owner: CadenceProduct Name: XCELIUMVersion: 21.09.013 (XCELIUMMAIN) *Supported Architectures: x86_64Website Home Page : www.cadence.comLanguages Supported: englishSystem Requirements: Linux *Size: 51.9 Gb 购买后，将显示帖子中所有出售内容。
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